Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10, which contains five terminals, is shown in FIG. 1. Memory cell 10 comprises semiconductor substrate 12 of a first conductivity type, such as P type. Substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of substrate 12. Between the first region 14 and the second region 16 is channel region 18. Bit line BL 20 is connected to the second region 16. Word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. Word line 22 has little or no overlap with the second region 16. Floating gate FG 24 is over another portion of channel region 18. Floating gate 24 is insulated therefrom, and is adjacent to word line 22. Floating gate 24 is also adjacent to the first region 14. Floating gate 24 may overlap the first region 14 to provide coupling from the first region 14 into floating gate 24. Coupling gate CG (also known as control gate) 26 is over floating gate 24 and is insulated therefrom. Erase gate EG 28 is over the first region 14 and is adjacent to floating gate 24 and coupling gate 26 and is insulated therefrom. The top corner of floating gate 24 may point toward the inside corner of the T-shaped erase gate 28 to enhance erase efficiency. Erase gate 28 is also insulated from the first region 14. Memory cell 10 is more particularly described in U.S. Pat. No. 7,868,375, whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. Memory cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on erase gate 28 with other terminals equal to zero volts. Electrons tunnel from floating gate 24 into erase gate 28 causing floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state.
Memory cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on coupling gate 26, a high voltage on source line 14, a medium voltage on erase gate 28, and a programming current on bit line 20. A portion of electrons flowing across the gap between word line 22 and floating gate 24 acquire enough energy to inject into floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in a read condition. The resulting cell programmed state is known as ‘0’ state.
Memory cell 10 is read in a Current Sensing Mode as following: A bias voltage is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias or zero voltage is applied on erase gate 28, and a ground is applied on source line 14. There exists a cell current flowing from bit line 20 to source line 14 for an erased state and there is insignificant or zero cell current flow from the bit line 20 to the source line 14 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Current Sensing Mode, in which bit line 20 is grounded and a bias voltage is applied on source line 24. In this mode the current reverses the direction from source line 14 to bitline 20.
Memory cell 10 alternatively can be read in a Voltage Sensing Mode as following: A bias current (to ground) is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias voltage is applied on erase gate 28, and a bias voltage is applied on source line 14. There exists a cell output voltage (significantly >0V) on bit line 20 for an erased state and there is insignificant or close to zero output voltage on bit line 20 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Voltage Sensing Mode, in which bit line 20 is biased at a bias voltage and a bias current (to ground) is applied on source line 14. In this mode, memory cell 10 output voltage is on the source line 14 instead of on the bit line 20.
The prior art also includes decoding circuitry for selecting an address within a memory array and selecting a bit line within the array. FIG. 5 depicts prior art memory system 500. Memory system 500 comprises array 530 and array 540, which typically are identical memory arrays of floating gate memory cells. Address lines 580 carry the address signals of the memory location to which the read or write operation applies. Address decoder 510 and address decoder 520 decode the address carried on address lines 580 and activate the appropriate word line and bit line in array 530 or array 540 so that a word of data is read from the correct location or a word of data is written to the correct location. As part of this operation, address decoder 510 controls bit line multiplexer 550, and address decoder 520 controls bit line multiplexer 560.
As an example, during a read operation of a particular address in array 530, the appropriate word line X and bit line Y will be activated in array 530, and bit line multiplexer 550 will output word 95 from that location in array 530 as an input to comparator 570. Concurrently, all word lines for array 540 are off, because the read operation does not involve array 540. The same bit line Y that was activated in array 530 is activated in array 540, and bit line multiplexer 560 outputs a word 96 from bit line Y as an input to comparator 570. Because no word line was activated for array 540, word 96 will not constitute data stored in array 540, but rather, represents a pre-charge voltage stored within bit line multiplexer 560. This voltage is used as a reference voltage by comparator 570. Comparator 570 will compare word 95 and word 96. One of ordinary skill in the art will understand that word 95 comprises one or more bits, and word 96 comprises one or more bits. Comparator 570 comprises a comparator circuit for each bit within word 95 and within word 96. That is, if word 95 and word 96 are 8 bits each, comparator 570 will comprise 8 comparator circuits, where each comparator circuit will compare one bit from word 95 with one bit at the same location within word 96. Output line 590 contains the result of the comparison of each bit pair.
If a bit within word 95 is higher than corresponding bit in word 96, then it is interpreted as a “1,” and outline line 590 will contain a “1” at that location. If a bit within word 95 is equal to or lower than corresponding bit in word 96, then it is interpreted as a “0,” and output line 590 will contain a “0” at that location.
One of ordinary skill in the art will appreciate that the prior art system of FIG. 5 contains two stages of multiplexors—address decoders 510 and 520 and bit line multiplexors 550 and 560. The ability to pre-charge bit lines is directly impacted by the number of stages of multiplexors involved in a read operation.
FIG. 6A shows the design of FIG. 5 in greater detail. Sense amplifier 600 comprises a first circuit coupled to selected memory cell 640 (which can be a cell in array 530) and a second circuit coupled to dummy cell 650 (which can be a cell in array 540). The first circuit comprises part of address MUX level 630 (which is a portion of address decoder 510), and the second circuit comprises part of address MUX level 630 (which is a portion of address decoder 520). The first circuit further comprises part of bit line MUX level 620 (which is a portion of bit line multiplexor 550), and the second circuit comprises part of dummy bit line MUX level 620 (which is a portion of bit line multiplexor 560). The first circuit further comprises PMOS transistors 601, 602, and 607, and second circuit further comprises PMOS transistors 608, 609, and 614.
The nodes IOR and DUMIOR are coupled to the inputs of comparator 615. The output of comparator 615 is coupled to inverter 616. The output of inverter 616 is coupled to buffer 617, which outputs the signal DOUT, which indicates the value stored in selected cell 640. In this prior art design, PMOS transistors 601 and 608 are not symmetrical.
FIG. 6B depicts certain operating characteristics of sense amplifier 600. Timing diagram 660 shows the behavior of PCHENB, DUMIOR, IOR, Pre_BL, and BL during a pre-charge operation, which typically occurs during a pre-charge period and precedes a read operation. As can be seen, the delay T1 is undesired and represents an unwanted increase in pre-charge time.
Diagram 670 shows the situation where selected cell 640 stores a “1.” Once the read operation commences, IOR will be pulled toward ground, below the pre-charge value of DUMIOR. Diagram 680 shows the situation where selected cell 640 stores a “0.” Once the read operation commences, IOR will be pulled toward VDD, above the pre-charge value of DUMIOR.
With flash memory systems becoming ubiquitous in all manner of computing and electronic devices, it is increasingly important to create designs that enable faster read and operations and that are able to pre-charge bit lines as fast as possible.